Transistors are core devices of integrated circuits. The formation of transistors typically involves implanting impurities into semiconductor substrates to form source and drain regions and lightly doped source and drain (LDD) regions. The implanted source and drain regions and LDD regions are then annealed so that the implanted impurities are activated and the defects caused by the implantation are reduced.
Conventionally, LDD regions of fin field-effect transistors (FinFETs) were formed by implanting impurities into portions of fins. FIG. 1 illustrates a cross-sectional view of a conventional LDD implantation process, wherein arrows represent the implanted impurity. In order to form LDD regions on the sidewalls of fin 10, the implantations are tilted with tilt angles θ greater than 0 degrees.
Since the circuits are highly compacted, there are other devices in the close proximity of fin 10. For example, fin 12 may be closely located from fin 10. Fins 10 and 12 may belong to FinFETs having different conductivity types. Therefore, when fin 10 is implanted, photo resist 14 is formed to mask fin 12. Since height H of photo resist 14 is typically much greater compared to height h of fin 10, the shadowing effect may occur, and photo resist 14 may block some of the impurity ions from reaching the lower portions of fin 10 if tilt angle θ is greater than a certain value (the illustrated angle θ in FIG. 1). On the other hand, the shadowing effect cannot be eliminated by reducing tilt angles θ since the reduction of tilt angles θ results in the reduction in the implantation depth, and the resulting LDD regions will become too shallow.
LDD regions may also be formed by depositing a boron silicate glass (BSG) layer or a phospho silicate glass (PSG) layer on a fin through a chemical vapor deposition step, and then performing an anneal so that the boron atoms in the BSG layer or the phosphorous atoms in the PSG layer may diffuse into the fin to form LDD regions. However, the anneal temperature needs to be higher than about 500° C., which is higher than the maximum temperature any photo resist can sustain. Accordingly, this process is incompatible with the use of photo resist.